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APW7067N
Synchronous Buck PWM and Linear Controller
Features
*
Provided Two Regulated Voltages - Synchronous Buck Converter - Linear Regulator
General Description
The APW7067N integrates synchronous buck PWM and linear controller, as well as monitoring and protection functions into a single package. The synchronous PWM controller drives dual N-channel MOSFETs, which provides one controlled power output with undervoltage and over-current protections. Linear controller drives an external N-channel MOSFET with under-voltage protection. The APW7067N provides excellent regulation for output load variation. An internal 0.8V temperature-compensated reference voltage is designed to meet the requirement of low output voltage applications. The switching frequency is adjustable from 150kHz to 1000kHz. The APW7067N with excellent protection functions: POR, OCP and UVP. The Power-On Reset (POR) circuit can monitor VCC12 supply voltage exceeds its threshold voltage while the controller is running, and a built-in digital soft-start provides both outputs with controlled rising voltage. The Over-Current Protection (OCP) monitors the output current by using the voltage drop across the lower MOSFET' RDS(ON), comparing s with internal VOCP (0.25V), eliminating the need for a current sensing resister. When the output current reaches the trip point, the controller will shutdown the IC directly, and latch the converter' output. The s Under-Voltage Protection (UVP) monitors the voltages of FB and FBL pins for short-circuit protection. When the VFB or VFBL is less than 50% of VREF, the controller will shutdown the IC directly.
* *
Single 12V Power Supply Required Excellent Both Output Voltage Regulation - 0.8V Internal Reference - 1% Over Line Voltage and Temperature
* * * * * * *
Integrated Soft-Start for PWM and Linear Outputs Programmable Frequency Range from 150 kHz to 1000kHz Voltage Mode PWM Control Design and Up to 89% (Typ.) Duty Cycle Under-Voltage Protection for PWM and Linear Output Over-Current Protection for PWM Output - Sense Low-Side MOSFET' RDS(ON) s SOP-14, QSOP-16 and QFN-16 packages Lead Free Available (RoHS Compliant)
Applications
*
Graphic Cards
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 1 www.anpec.com.tw
APW7067N
Pinouts
FS_DIS UGATE 14
BOOT 1 FS_DIS 2 COMP 3 FB 4 DRIVE 5 FBL 6 GND 7 SOP-14 TOP VIEW
14 UGATE 13 PHASE 12 PGND 11 LGATE 10 NC 9 NC 8 VCC12
BOOT 1 FS_DIS 2 COMP 3 FB 4 DRIVE 5 FBL 6 GND 7 GND 8 QSOP-16 TOP VIEW
16 UGATE 15 PHASE 14 PGND 13 LGATE 12 NC 11 NC 10 VCC12 9 VCC12
16 COMP FB DRIVE FBL 1 2 3 4 5 AGND
15
13 12 PGND LGATE NC NC
Metal GND Pad (Bottom)
PHASE 11 10 9 8 VCC12
6 DGND
BOOT
7 VCC12
QFN-16 TOP VIEW
Ordering and Marking Information
APW7067N
Lead Free Code Handling Code Temp. Range Package Code Package Code K : SOP - 14 M : QSOP - 16 QA : QFN - 16 Temp. Range E : -20 to 70 C Handling Code TU : Tube TR : Tape & Reel TY : Tray (for QFN only) Lead Free Code L : Lead Free Device Blank : Original Device XXXXX - Date Code
APW7067N K :
APW7067N XXXXX APW7067N XXXXX
APW7067N M :
XXXXX - Date Code
APW7067N Q :
APW7067N XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS and compatible with both SnPb and lead-free soldering operations. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J STD-020C for MSL classification at lead-free peak reflow temperature.
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APW7067N
Block Diagram
VCC12
Regulator
Power-On Reset Sense Low Side
BOOT UGATE
GND
VREF 10V (0.8V) 50%VREF :2 U.V.P Comparator Soft Start and Fault Logic
O.C.P Comparator VOCP 0.25V
PHASE
Gate Control
LGATE PGND
Error Amp 1 PWM Comparator U.V.P Comparator
FBL :2
50%VREF 10V
VREF Oscillator Sawtooth wave VREF Error Amp 2
DRIVE
FB
COMP
FS_DIS
Absolute Maximum Ratings
Symbol VCC12 BOOT UGATE LGATE PHASE DRIVE VCC12 to GND BOOT to PHASE UGATE to PHASE <400ns pulse width >400ns pulse width LGATE to PGND PHASE to GND DRIVE to GND <400ns pulse width >400ns pulse width <400ns pulse width >400ns pulse width Parameter Rating -0.3 to +16 -0.3 to +16 -5 to BOOT+5 -0.3 to BOOT+0.3 -5 to VCC12+5 -0.3 to VCC12+0.3 -5 to +21 -0.3 to 16 12 -0.3 to 7 Unit V V V V V V V
FB, FBL, COMP, FB, FBL, COMP, FS_DIS to GND FS_DIS
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APW7067N
Absolute Maximum Ratings (Cont.)
Symbol PGND TJ TSTG TSDR VESD PGND to GND Junction Temperature Range Storage Temperature Soldering Temperature (10 Seconds) Minimum ESD Rating Parameter Rating -0.3 to +0.3 -20 to +150 -65 ~ 150 300 2 Unit V C C C KV
NOTE1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. NOTE2: The device is ESD sensitive. Handling precautions are recommended.
Recommended Operating Conditions
Symbol VCC12 VIN1 VOUT1 IOUT1 IOUT2 TA TJ IC Supply Voltage Converter Input Voltage Converter Output Voltage Converter Output Current Linear Output Current Ambient Temperature Range Junction Temperature Range Parameter Rating 10.8 to 13.2 2.9 to 13.2 0.9 to 5 0 to 30 0 to 3 -20 to 70 -20 to 125 Unit V V V A A C C
Electrical Characteristics
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70C. Typical values are at TA = 25C.
Symbol
Parameter
Test Conditions
APW7067N Min Typ Max
Unit
INPUT SUPPLY CURRENT VCC12 Supply Current (Shutdown mode) VCC12 Supply Current POWER-ON RESET Rising VCC12 Threshold Falling VCC12 Threshold 7.7 7.2 7.9 7.4 8.1 7.6 V V UGATE, LGATE and DRIVE open; FS_DIS = GND UGATE, LGATE and DRIVE open; FOSC = 600kHz 4 16 6 24 mA mA
ICC12
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APW7067N
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70C. Typical values are at TA = 25C.
Symbol OSCILLATOR Accuracy FOSC FOSC VOSC Duty VREF
Parameter
Test Conditions
APW7067N Min Typ Max
Unit
-15 RFS_DIS = 110k ohms RFS_DIS = 47k ohms (nominal 1.2V to 2.7V) (NOTE3) 255 510 300 600 1.5 89 for Error Amp1 and Amp2 IOUT1 = 0 to 10A IOUT2 = 0 to 3A 0.792 -1 0.80
+15 345 690
% kHz kHz V %
Oscillator Frequency Oscillator Frequency Ramp Amplitude Maximum Duty Cycle Reference Voltage Reference Voltage Tolerance PWM Load Regulation Linear Load Regulation
REFERENCE 0.808 +1 % 1 % 1 % 93 20 8 0.1 5 0 COMP = 2V COMP = 2V 12 12 2.5 2 2.5 3.5 2.25 0.7 2.25 0.4 20 3.375 1.05 3.375 0.6 1 V % % %
PWM ERROR AMPLIFIER Gain SR Open Loop Gain Slew Rate FB Input Current VCOMP COMP High Voltage VCOMP COMP Low Voltage ICOMP ICOMP IUGATE IUGATE ILGATE ILGATE COMP Source Current COMP Sink Current Upper Gate Source Current Upper Gate Sink Current Lower Gate Source Current Lower Gate Sink Current RL = 10k, CL = 10pF (NOTE3) RL = 10k, CL = 10pF (NOTE3) RL = 10k, CL = 10pF (NOTE3) VFB = 0.8V
dB MHz V/us uA V V mA mA A A A A nS
GBWP Open Loop Bandwidth
GATE DRIVERS BOOT = 12V, UGATE-PHASE = 2V VCC12 = 12V, LGATE = 2V
RUGATE Upper Gate Source Impedance BOOT = 12V, IUGATE = 0.1A RUGATE Upper Gate Sink Impedance RLGATE Lower Gate Sink Impedance TD Dead Time BOOT = 12V, IUGATE = 0.1A VCC12 = 12V, ILGATE = 0.1A RLGATE Lower Gate Source Impedance VCC12 = 12V, ILGATE = 0.1A
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APW7067N
Electrical Characteristics (Cont.)
Unless otherwise specified, these specifications apply over VCC12 = 12V, and TA =-20 ~ 70C. Typical values are at TA = 25C.
Symbol
Parameter
Test Conditions
APW7067N Min Typ 70 19 6 0.1 10 0 1 Max
Unit
LINEAR REGULATOR Gain SR VDRIVE VDRIVE IDRIVE IDRIVE Open Loop Gain Slew Rate FBL Input Current DRIVE High Voltage DRIVE Low Voltage DRIVE Source Current DRIVE Sink Current FB Under Voltage Protection Trip Point FBL Under Voltage Protection Trip Point OCP Voltage FOSC = 600kHz FOSC = 300kHz DRIVE = 5V DRIVE = 5V RL = 10k, CL = 10pF (NOTE3) RL = 10k, CL = 10pF (NOTE3) RL = 10k, CL = 10pF (NOTE3) VFBL= 0.8V dB MHz V/us uA V V mA mA GBWP Open Loop Bandwidth
4 3
PROTECTION VFB-UV VFBL-UV VOCP Percent of VREF Percent of VREF 230 50 50 250 2.1 4.2 270 % % mV ms ms
SOFT START TSS Internal Soft-Start Interval (NOTE3)
NOTE3: Guaranteed by design.
Typical Application Circuit
C1
2.2nF
VIN1 Q3 ON/OFF
2N7002 12V
CIN1 Q1
APM2509 470uFx2
R2
3.9K
C2
0.01uF
VOUT1 R3
22
R1
1.5K
C4
0.1uF
L
1uH
VOUT1
1.2V
C3
22nF
RFS_DIS VIN2
3.3V
1 2 3 4
BOOT FS_DIS COMP FB DRIVE FBL GND
UGATE PHASE PGND LGATE NC NC VCC12
14 13 12 Q2 11 10 9 8 C7
1uF 12V APM2506
RGND1
3K
COUT1
470uFx2
C6
2.2nF
CIN2
470uF
Q4
APM3055
5 C5 R5 6 R4 7
R6
2.2
R7
2.2
VOUT2
2.5V 2.5K
APW7067N
RGND2
1.17K
COUT2
470uF
* C5, R5 for specific application
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APW7067N
Function Pin Descriptions
VCC12 Power supply input pin. Connect a nominal 12V power supply to this pin. The power-on reset function monitors the input voltage at this pin. It is recommended that a decoupling capacitor (1 to 10F) be connected to GND for noise decoupling. BOOT This pin provides the bootstrap voltage to the upper gate driver for driving the N-channel MOSFET. An external capacitor from PHASE to BOOT, an internal diode, and the power supply valtage VCC12, generates the bootstrap voltage for the upper gate diver (UGATE). PHASE This pin is the return path for the upper gate driver. Connect this pin to the upper MOSFET source, and connect a capacitor to BOOT for the bootstrap voltage. This pin is also used to monitor the voltage drop across the lower MOSFET for over-current protection. GND This pin is the signal ground pin. Connect the GND pin to a good ground plane. PGND This pin is the power ground pin for the lower gate driver. It should be tied to GND pin on the board. COMP This pin is the output of PWM error amplifier. It is used to set the compensation components. FB This pin is the inverting input of the PWM error amplifier. It is used to set the output voltage and the compensation components. This pin is also monitored for undervoltage protection, when the FB voltage is under 50% of reference voltage (0.4V), both outputs will be shut FS_DIS This pin be allowed to adjust the switching frequency. Connect a resistor from FS_DIS pin to the ground to increase the switching frequency. This pin also provides shutdown function, use an open drain logic signal to pull this pin low to disable both outputs, leave open to enable both outputs. - downed immediately. UGATE This pin is the gate driver for the upper MOSFET of PWM output. LGATE This pin is the gate driver for the lower MOSFET of PWM output. DRIVE This pin drives the gate of an external N-channel MOSFET for linear regulator. It is also used to set the compensation for some specific applications, for example, with low values of output capacitance and ESR. FBL This pin is the inverting input of the linear regulator error amplifier. It is used to set the output voltage. This pin is also monitored for under-voltage protection, when the FBL voltage is under 50% of reference voltage (0.4V), both outputs will be shutdown immediately.
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APW7067N
Typical Characteristics
Power On
VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V, L=1uH
Power Off
VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V, L=1uH
CH1
CH1
CH2
CH2
CH3
CH3
CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Vo2 (2V/div) Time: 5ms/div
CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Vo2 (2V/div) Time: 5ms/div
EN
VCC12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH
Shutdown(FS_DIS=GND)
Vcc12=12V, Vin1=12V,Vin2=3.3V Vo1=1.2V,Vo2=2.5V,L=1uH
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: Vo1 (1V/div) CH4: Vo2 (2V/div) Time: 5ms/div
CH1: FS_DIS (1V/div) CH2: Drive (5V/div) CH3: Vo1 (1V/div) CH4: Vo2 (2V/div) Time: 5ms/div
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APW7067N
Typical Characteristics (Cont.)
UGATE Rising
Vcc12=12V, Vin1=12V, Vo1=1.2V
UGATE Falling
Vcc12=12V, Vin1=12V, Vo1=1.2V
CH1
CH1
CH2
CH2
CH3
CH3
CH1: Ug (20V/div) CH2: Phase (10V/div) CH3: Lg (10V/div) Time: 50ns/div
CH1: Ug (20V/div) CH2: Phase (10V/div) CH3: Lg (10V/div) Time: 50ns/div
UVP_PWM Controller(FB< 0.4V)
VCC12=12V, Vin1=12V Vo1=1.2V, L=1uH, Io1=10A
UVP_Linear Regulator(FBL< 0.4V)
VCC12=12V, Vin2=3.3V Vo2=2.5V, Io2=3A
CH1 CH1
CH2 CH3 CH2
CH4
CH3
CH1: FB (1V/div) CH2: Vo1 (1V/div) CH3: Ug (20V/div) CH4: COMP (5V/div) Time: 50us/div
CH1: FBL (1V/div) CH2: Drive (5V/div) CH3: Vo2 (2V/div) Time: 100us/div
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APW7067N
Typical Characteristics (Cont.)
Load Transient Response(PWM Controller) - VCC12=12V, Vin1=12V, Vo1=2V, Fosc=300KHz - Io1 slew rate= O 10 A/us
Io1=0Aa10A Io1=0Aa10Aa0A Io1=10Aa0A
CH1
CH1
CH1
CH2
CH2
CH2
CH3
CH3
CH3
CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) Time: 20us/div
CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) Time: 50us/div
CH1: Vo1 (100mV/div,AC) CH2: Ug (20V/div) CH3: Io1(10A/div) Time: 20us/div
Load Transient Response(Linear Regulator) - VCC12=12V, Vin2=3.3V, Vo2=2.5V - Io2 slew rate= O 3A/us
Io2=0Aa3A Io2=0Aa3Aa0A Io2=3Aa0A
CH1
CH1
CH1
CH2
CH2
CH2
CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) Time: 1us/div
CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) Time: 10us/div
CH1: Vo2 (100mV/div,AC) CH2: Io2(2A/div) Time: 1us/div
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APW7067N
Typical Characteristics (Cont.)
Over Current Protection
VCC12=12V, Vin1=12V, Vo1=1.2V, L=1uH, Co=470uH*2, L_Side_Rds(on)=17m[
Short Test after Power Ready
VCC12=12V, Vin1=12V, Vo1=1.2V, L=1uH, Co=470uH*2, L_Side_Rds(on)=17m[
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH4
CH1: Vo1 (1V/div) CH2: Drive (5V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 50us/div
CH1: Vo1 (1V/div) CH2: Drive (5V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 50us/div
Short Test before Power On
VCC12=12V, Vin1=12V,Vo1=1.2V, L=1uH, Co=470uH*2, L_Side_Rds(on)=17m[
0.804
VREF vs. Junction Temperature
0.8035
Reference Voltage(V)
CH1
0.803
CH2
0.8025
0.802
VREF
0.8015
CH3
0.801
0.8005
CH4
-40
-20
0
20
40
60
80
100
120
CH1: VCC12 (10V/div) CH2: Vo1 (1V/div) CH3: Ug (20V/div) CH4: IL (10A/div) Time: 2ms/div
Junction Temperature (C)
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APW7067N
Typical Characteristics (Cont.)
UGATE Source Current vs. UGATE Voltage
3
UGATE Sink Current vs. UGATE Voltage
3.5 3
UGATE Source Current (A)
2.5
VBOOT=12V
2
UGATE Sink Current (A)
2.5 2 1.5 1 0.5 0
VBOOT=12V
Phase=0V
Phase=0V
1.5
1
0.5
0 0 2 4 6 8 10 12
0
0.5
1
1.5
2
2.5
3
UGATE Voltage (V)
UGATE Voltage (V)
LGATE Source Current vs. LGATE Voltage
3
LGATE Sink Current vs. LGATE Voltage
7 6
2.5
LGATE Source Current (A)
VCC=12V
VCC=12V
LGATE Sink Current (A)
0 2 4 6 8 10 12
5 4 3 2 1 0 0 1 2 3 4
2
1.5
1
0.5
0
LGATE Voltage (V)
LGATE Voltage(V)
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APW7067N
Function Descriptions
Power On Reset (POR) The Power-On Reset (POR) function of APW7067N continually monitors the input supply voltage (VCC12), ensures the supply voltage exceed its rising POR threshold voltage. The POR function initiates soft-start interval operation while VCC12 voltages exceed their POR threshold and inhibits operation under disabled status. Soft-Start Figure 1. shows the soft-start interval. When VCC12 reaches the rising POR threshold voltage, the internal reference voltage is controlled to follow a voltage proportional to the soft-start voltage. The soft-start interval is variable by the oscillator frequency. The formulation is given by:
Voltage(V)
Voltage(V)
VCC12
POR
VOUT1 VOUT2
t0
t1
t2
Time
Figure 1. Soft-Start Interval
TSS = ( t 2 - t1) =
1 FOSC
x 1280
FB
Figure 2. shows more detail of the FB and FBL voltage ramps. The FB and FBL voltage soft-start ramps are formed with many small steps of voltage. The voltage of one step is about 20mV in FB and FBL, and the period of one step is about 32/FOSC. This method provides a controlled voltage rise and prevents the large peak current to charge the output capacitors. The FB voltage compares the FBL voltage to shift to an earlier time the establishment as Figure2. The voltage estabilishment time difference for FB and FBL is variable by the oscillator. The formulation is given by: Over-Current Protection The over-current protection monitors the output current by using the voltage drop across the lower MOSFET' s
t3 t4 Time 32/Fosc 20mV 20mV 32/Fosc FBL
Figure 2. The Controlled Stepped FB and FBL Voltage during Soft-Start
(t 4 - t3) =
1 FOSC
x 320 =
1 x TSS 4
RDS(ON) and this voltage drop will be compared with the internal 0.25V reference voltage. When the voltage drop across the lower MOSFET' RDS(ON) is larger than 0.25V, s an over-current condition is detected, the controller will shutdown the IC directly, and latch the converter's output.
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APW7067N
Function Descriptions
Over-Current Protection (Cont.) The threshold of the over current limit is given by:
VOCP (0.25V) = R DS(ON) (Low _ Side )
shutdown the APW7067N PWM controller. In shutdown mode, the UGATE and LGATE turn off and pull to PHASE and GND respectively.
ILIMIT
Switching Frequency The APW7067N provides the adjustable oscillator
For the over-current is never occurred in the normal operating load range; the variation of all parameters in the above equation should be determined. - The MOSFET' RDS(ON) is varied by temperature s and gate to source voltage, the user should deter mine the maximum RDS(ON) in manufacture' s datasheet. - The minimum VOCP should be used in the above equation. - Note that the ILIMIT is the current flow through the lower MOSFET; ILIMIT must be greater than maximum output current add the half of inductor ripple current. Under Voltage Protection
switching frequency . The switching frequency is determined by the value of RFS_DIS (from FS_DIS pin to GND), the adjustable range from150kHz to 1000kHz . Figure 3. shows how to select the resistor for the desired frequency. If the IC is operated in higher frequencies (ex. 600 kHz or above), the slope of the curve is steep, and a small change in resistance will have a big effect on the frequency. At lower frequencies, the slope of the curve is much less steep, even a large change in resistor value doesn' change the frequency too much. Figure 4. t shows more detail for the higher frequency and Figure5. shows the lower frequency.
1600
The FB and FBL pin are monitored during converter operation by their own Under Voltage (UV) comparator. If the FB or FBL voltage drop below 50% of the
Fosc(KHz)
1400
1200
1000
reference voltage (50% of 0.8V = 0.4V), a fault signal is internally generated, and the device turns off both high-side and low-side MOSFET and the converter' s output is latched to be floating. Shutdown and Enable Pulling the FS_DIS voltage to GND by an open drain transistor, shown in typical application circuit,
800
600
400
200
0 0 100 200 300 400 R ( K) 500 600 700 800
Figure 3. Oscillator Frequency vs. R
FS-DIS
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APW7067N
Function Descriptions (Conts)
Switching Frequency (Cont.) 1200
500
450
1000 Fosc(KHz)
Fosc(KHz)
400
350
800
300
250
600
200
150
400 0
100
10
20
30
40 50 R(K[)
60
70
80
50
150
250
350
450 R(K[)
550
650
750
Figure 4. Oscillator Frequency vs.R
FS-DIS
Figure 5. Oscillator Frequency vs.R
FS-DIS
(High Frequency)
(Low Frequency)
Application Information
Output Voltage Selection The output voltage of PWM converter can be programmed with a resistive divider. Use 1% or better resistors for the resistive divider is recommended. The FB pin is the inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by: Where R4 is the resistor connected from VOUT2 to FBL and RGND2 is the resistor connected from FBL to GND. Linear Regulator Input/Output Capacitor Selection The input capacitor is chosen based on its voltage rating. Under load transient condition, the input capacitor will momentarily supply the required transient current. The output capacitor for the linear regulator is chosen to minimize any droop during load transient condition. In addition, the capacitor is chosen based on its voltage rating. Linear Regulator Input/Output MOSFET Selection The maximum DRIVE voltage is about 10V when VCC12 is equal 12V. Since this pin drives an external N-channel MOSFET, therefore the maximum output voltage of the linear regulator is dependent upon the VGS. VOUT2MAX = 10 - VGS
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R1 VOUT1 = 0.8 x 1 + R GND1
Where R1 is the resistor connected from VOUT1 to FB and RGND1 is the resistor connected from FB to GND. The linear regulator output voltage VOUT2 is also set by means of an external resistor divider. The FBL pin is the inverter input of the error amplifier, and the reference voltage is 0.8V. The output voltage is determined by:
R4 VOUT2 = 0.8 x 1 + R GND2

APW7067N
Application Information (Conts)
Another criterion is its efficiency of heat removal. The power dissipated by the MOSFET is given by: Pd = IOUT2 x (VIN2 - VOUT2 ) Where IOUT2 is the maximum load current, VOUT2 is the nominal output voltage. In some applications, heatsink might be required to help maintain the junction temperature of the MOSFET below its maximum rating.
FLC
PHASE L OUTPUT1
COUT1 ESR
Figure 6. The Output LC Filter
Linear Regulator Compensation Selection
-40dB/dec
The linear regulator is stable over all loads current. However, the transient response can be further enhanced by connecting a RC network between the FBL and DRIVE pin. Depending on the output capacitance and load current of the application, the value of this RC network is then varied. PWM Compensation The output LC filter of a step down converter introduces a double pole, which contributes with -40dB/decade gain slope and 180 degrees phase shift in the control loop. A compensation network among COMP, FB and VOUT1 should be added. The compensation network is shown in Fig. 9. The output LC filter consists of the output inductor and output capacitors. The transfer function of the LC filter is given by:
Frequency(Hz) GAIN (dB) FESR -20dB/dec
Figure 7. The LC Filter GAIN and Frequency The PWM modulator is shown in Figure 8. The input is the output of the error amplifier and the output is the PHASE node. The transfer function of the PWM modulator is given by:
GAINPWM =
VIN VOSC
Driver
VIN1
GAINLC =
1 + s x ESR x COUT1 s2 x L x COUT1 + s x ESR x COUT1 + 1
OSC G VOSC PWM Comparator
The poles and zero of this transfer functions are:
FLC = 1 2 x x L x C OUT1
Output of Error Amplifier Driver
PHASE
FESR
1 = 2 x x ESR x C OUT1
Figure 8. The PWM Modulator The compensation network is shown in Figure 9. It provides a close loop transfer function with the highest zero crossover frequency and sufficient phase margin.
The FLC is the double poles of the LC filter, and FESR is the zero introduced by the ESR of the output capacitor.
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APW7067N
Application Information (Cont.)
PWM Compensation (Cont.) The transfer function of error amplifier is given by:
1 1 // R2 + VCOMP sC1 sC2 = = VOUT1 1 R1// R3 + sC3
1.Choose a value for R1, usually between 1K and 5K. 2.Select the desired zero crossover frequency FO: (1/5 ~ 1/10) X FS >FO>FESR Use the following equation to calculate R2:
R2 = VOSC F x O x R1 VIN FLC
GAINAMP
1 1 s + x s + (R1 + R3 ) x C3 R2 x C2 R1 + R3 = x C1 + C2 1 R1 x R3 x C1 s s + x s + R2 x C1 x C2 R3 x C3
3.Place the first zero FZ1 before the output LC filter double pole frequency FLC. FZ1 = 0.75 X FLC Calculate the C2 by the equation:
C2 = 1 2 x x R2 x FLC x 0.75
The poles and zeros of the transfer function are:
F Z1 = 1 2 x x R2 x C2
FZ2
1 = 2 x x (R1 + R3 ) x C3
FP1 =
FP2
1 C1 x C2 2 x x R2 x C1 + C2 1 = 2 x x R3 x C3
C1 R3 C3 R2 C2
4.Set the pole at the ESR zero frequency FESR: FP1 = FESR Calculate the C1 by the equation:
C1 =
C2 2 x x R2 x C2 x FESR - 1
VOUT1 R1 FB VREF VCOMP
5.Set the second pole FP2 at the half of the switching frequency and also set the second zero FZ2 at the output LC filter double pole FLC. The compensation gain should not exceed the error amplifier open loop gain, check the compensation gain at FP2 with the capabilities of the error amplifier. FP2 = 0.5 X FS FZ2 = FLC Combine the two equations will get the following component calculations:
R3 = R1 FS -1 2 x FLC
Figure 9. Compensation Network The closed loop gain of the converter can be written as: GAINLC X GAINPWM X GAINAMP Figure 10. shows the asymptotic plot of the closed loop converter gain, and the following guidelines will help to design the compensation network. Using the below guidelines should give a compensation similar to the curve plotted. A stable closed loop has a -20dB/ decade slope and a phase margin greater than 45 degree.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006 17
C3 =
1 x R3 x FS
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APW7067N
Application Information (Cont.)
PWM Compensation (Cont.) starting point is to choose the ripple current to be approximately 30% of the maximum output current.
FZ1 FZ2 FP1 FP2
Once the inductance value has been chosen, select an inductor that is capable of carrying the required peak current without going into saturation. In some
Compensation Gain
GAIN (dB)
20log (R2/R1)
types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This will result in a larger output ripple voltage.
20log (VIN/GVOSC)
FLC FESR PWM & Filter Gain Frequency(Hz) Converter Gain
Output Capacitor Selection Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Therefore, selecting high performance low ESR capacitors is intended for switching regulator applications. In some applications, multiple capacitors have to be parallel to achieve the desired ESR value. A small decoupling capacitor in parallel for bypassing the noise is also recommended, and the voltage rating of the output capacitors also must be considered. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, select the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT1/2, where IOUT1 is the load current. During power up, the input capacitors have to handle large amount of surge current. If tantalum capacitors are used, make sure they are surge tested by the manufactures. If in doubt, consult the capacitors manufacturer. For high frequency decoupling, a ceramic capacitor 1uF can be connected between the drain of upper MOSFET and the source of lower MOSFET.
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Figure 10. Converter Gain and Frequency Output Inductor Selection The inductor value determines the inductor ripple current and affects the load transient response. Higher inductor value reduces the inductor' ripple current and s induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by:
IRIPPLE =
VIN1 - VOUT1 VOUT1 x FS x L VIN1
VOUT1 = IRIPPLE x ESR
where Fs is the switching frequency of the regulator. Although increase of the inductor value and frequency reduces the ripple current and voltage, a tradeoff will exist between the inductor' ripple current and the s regulator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (FS) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFET and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006
APW7067N
Application Information (Cont.)
MOSFET Selection The selection of the N-channel power MOSFETs are determined by the RDS(ON), reverse transfer capacitance (CRSS) and maximum output current requirement. There are two components of loss in the MOSFETs: conduction loss and transition loss. For the upper and lower MOSFET, the losses are approximately given by the following: PUPPER = IOUT1 (1+ TC)(RDS(ON))D + (0.5)( IOUT1)(VIN1)( tSW)FS PLOWER = IOUT1 (1+ TC)(RDS(ON))(1-D) Where IOUT1 is the load current TC is the temperature dependency of RDS(ON) FS is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction loss while the upper MOSFET include an additional transition loss. The switching internal, tSW , is a function of the reverse transfer capacitance C RSS. The (1+TC) term is to factor in the temperature dependency of the RDS(ON) and can be extracted from the "RDS(ON) vs Temperature" curve of the power MOSFET. Layout Considerations In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at 300KHz or above, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is free-wheeling by the lower MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short, wide printed circuit
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traces should minimize interconnecting impedances and the magnitude of voltage spike. And signal and power grounds are to be kept separate till combined using ground plane construction or single point grounding. Figure 11. illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: - The metal plate of the bottom of the packages (QFN-16) must be soldered to the PCB and connected to the GND plane on the backside through several thermal vias. - Keep the switching nodes (UGATE, LGATE and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible. - The traces from the gate drivers to the MOSFETs (UG, LG, DRIVE) should be short and wide. - Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. - Decoupling capacitor, compensation component, the resistor dividers and boot capacitors should be close their pins. (For example, place the decoupling ceramic capacitor near the drain of the high-side MOSFET as close as possible. The bulk capacitors are also placed near the drain). - The input capacitor should be near the drain of the upper MOSFET; the output capacitor should be near the loads. The input capacitor GND should be close to the output capacitor GND and the lower
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APW7067N
Application Information (Cont.)
Layout Considerations (Cont.) MOSFET GND. - The drain of the MOSFETs (VIN1 and PHASE nodes) should be a large plane for heat sinking.
APW7067N VIN1 VCC12 VIN2 BOOT DRIVE VOUT2
L O A D
UGATE PHASE LGATE
L O A D
FBL
VOUT1
Figure 11. Layout Guidelines
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006
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APW7067N
Package Information
SOP - 14 (150mil)
E
H
0.015 x 45
D
C
A e B
GAUGE PLANE SEATING PLANE
A1
0.010
L
Dim A A1 B C D E e H L
Millimeters Min. 1.477 0.102 0.331 0.191 8.558 3.82 1.274 5.808 0.382 0 6.215 1.274 8 0.228 0.015 0 Max. 1.732 0.255 0.509 0.2496 8.762 3.999 Min. 0.058 0.004 0.013 0.0075 0.336 0.150
Inches Max. 0.068 0.010 0.020 0.0098 0.344 0.157 0.050 0.244 0.050 8
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006
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APW7067N
Package Information
QSOP-16
D
E
E1
GAUGE PLANE
1
2
3
A e b A1
L
1
Millimeters Dim A A1 b D E E1 e L 1 Min. 1.35 0.10 0.20 4.80 5.79 3.81 0.635 TYP. 0.41 0 1.27 8 0.016 0 Max. 1.75 0.25 0.30 5.00 6.20 3.99 Min. 0.053 0.004 0.008 0.189 0.228 0.150
Inches Max. 0.069 0.010 0.012 0.197 0.244 0.157 0.025 TYP. 0.050 8
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006
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APW7067N
Package Information
QFN-16
D
e
b
E
E2
L
D2 A2 A3
Dim A A1 A2 A3 D E b D2 E2 e L
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006
A
A1
Millimeters Min. 0.76 0.00 0.57 0.20 REF. 3.90 3.90 0.25 2.05 2.05 0.650 BSC 0.50 0.60 0.002 4.10 4.10 0.35 2.15 2.15 0.154 0.154 0.010 0.081 0.081 0.0257BSC 0.024 Max. 0.84 0.04 0.63 Min. 0.030 0.00 0.022 0.008 REF. 0.161 0.161 0.014 0.085 0.085 Inches Max. 0.033 0.0015 0.025
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APW7067N
Physical Specifications
Terminal Material Lead Solderability Solder-Plated Copper (Solder Material : 90/10 or 63/37 SnPb), 100%Sn Meets EIA Specification RSI86-91, ANSI/J-STD-002 Category 3.
Reflow Condition
TP
(IR/Convection or VPR Reflow)
tp Critical Zone T L to T P
Ramp-up
Temperature
TL Tsmax
tL
Tsmin Ramp-down ts Preheat
25
t 25 C to Peak
Tim e
Classification Reflow Profiles
Profile Feature Average ramp-up rate (TL to TP) Preheat - Temperature Min (Tsmin) - Temperature Max (Tsmax) - Time (min to max) (ts) Time maintained above: - Temperature (TL) - Time (tL) Peak/Classificatioon Temperature (Tp) Time within 5C of actual Peak Temperature (tp) Ramp-down Rate Sn-Pb Eutectic Assembly 3C/second max. 100C 150C 60-120 seconds 183C 60-150 seconds See table 1 10-30 seconds Pb-Free Assembly 3C/second max. 150C 200C 60-180 seconds 217C 60-150 seconds See table 2 20-40 seconds
6C/second max. 6C/second max. 6 minutes max. 8 minutes max. Time 25C to Peak Temperature Notes: All temperatures refer to topside of the package .Measured on the body surface.
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APW7067N
Classification Reflow Profiles (Cont.)
Table 1. SnPb Entectic Process - Package Peak Reflow Temperatures 3 3 Package Thickness Volum e m m Volume mm <350 350 <2.5 m m 240 +0/-5C 225 +0/-5C 2.5 m m 225 +0/-5C 225 +0/-5C Table 2. Pb-free Process - Package Classification Reflow Temperatures 3 3 3 Package Thickness Volume mm Volume mm Volume mm <350 350-2000 >2000 <1.6 m m 260 +0C* 260 +0C* 260 +0C* 1.6 m m - 2.5 m m 260 +0C* 250 +0C* 245 +0C* 2.5 m m 250 +0C* 245 +0C* 245 +0C* *Tolerance: The device manufacturer/supplier shall assure process compatibility up to and including the stated classification temperature (this means Peak reflow temperature +0C. For example 260C+0C) at the rated MSL level.
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TST ESD Latch-Up Method MIL-STD-883D-2003 MIL-STD-883D-1005.7 JESD-22-B,A102 MIL-STD-883D-1011.9 MIL-STD-883D-3015.7 JESD 78 Description 245C, 5 SEC 1000 Hrs Bias @125C 168 Hrs, 100%RH, 121C -65C~150C, 200 Cycles VHBM > 2KV, VMM > 200V 10ms, 1 tr > 100mA
Carrier Tape & Reel Dimensions
t P P1 D
Po E
F W
Bo
Ao
Ko D1
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006
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APW7067N
Carrier Tape & Reel Dimensions (Cont.)
T2
J C A B
T1
Application
SOP-14 (150mil) Application
A 330REF F 7.5 A 330 1
B 100REF D
C 13.0 + 0.5 - 0.2 D1
J 2 0.5 Po 4.0 J
T1 16.5REF P1 2.0 T1 12.4 0.2 P1 2.0 0.1
T2
W
P 8 t 0.30.05 P 8 0.1 Ko
E 1.75
2.5 025 16.0 0.3 Ao 6.5 T2 2 0.2 Ao 6.4 0.1 Ko 2.10 W 12 0. 3 Bo 5.2 0. 1
0.50 + 0.1 1.50 (MIN) B 62 +1.5 D 1.55 +0.1 C
E 1.750.1 t
12.75+ 0.15 2 0.5 D1 Po
QSOP- 16
F 5.5 1
1.55+ 0.25 4.0 0.1
2.1 0.1 0.30.013
(mm)
4x4 Shipping Tray
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Jun., 2006
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APW7067N
4x4 Shipping Tray(Cont.)
Cover Tape Dimensions
Application SOP- 14 QSOP- 16 Carrier Width 24 12 Cover Tape Width 21.3 9.3 Devices Per Reel 2500 2500
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 7F, No. 137, Lane 235, Pac Chiao Rd., Hsin Tien City, Taipei Hsien, Taiwan, R. O. C. Tel : 886-2-89191368 Fax : 886-2-89191369
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